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MAX2769
Universal GPS Receiver
STRM_EN
PIN 21
I
ADC
OUTPUT
DRIVER
PIN 20
PIN 17
Q
BIT 0
BIT 1
BIT 2
BIT 3
DATA_OUT
CLK_SER
DATA_SYNC
PIN 18
TIME_SYNC
STRM_EN
STRM_START
STRM_STOP
STRM_EN
CONTROL
SIGNALS
FROM 3-WIRE
INTERFACE
STRM_COUNT<2:0>
DIEID<1:0>
STRM_BITS<1:0>
FRM_COUNT<27:0>
STAMP_EN
DAT_SYNCEN
TIME_SYNCEN
STRM_RST
CLK_ADC
CLK_SER
ADCCLK_SEL
L_CNT<11:0>
M_CNT<11:0>
REF/XTAL
PIN 15
THROUGH
/2
CLK_IN
CLK_OUT
/4
x2
FRCLK_SEL
SERCLK_SEL
REFDIV<1:0>
Figure 3. DSP Interface Top-Level Connectivity and Control Signals
ter. This selects between bit 0 ; bit 0 and bit 1 ; bit 0 and bit 2 ;
and bit 0 , bit 1 , bit 2 , and bit 3 cases. If only bit 0 is serial-
ized, the data stream consists of bit 0 data only. If a seri-
alization of bit 0 and bit 1 (or bit 2 ) is selected, the stream
data pattern consists of 16 bits of bit 0 data followed by
16 bits of bit 1 (or bit 2 ) data, which, in turn, is followed by
16 bits of bit 0 data, and so on. In this case, the serial
clock must be at least twice as fast as the ADC clock. If a
4-bit serialization of bit 0 , bit 1 , bit 2 , and bit 3 is chosen, the
serial clock must be at least four times faster than the
ADC clock.
The ADC data is loaded in parallel into four holding reg-
isters that correspond to four ADC outputs. Holding reg-
isters are 16 bits long and are clocked by the ADC clock.
14
At the end of the 16-bit ADC cycle, the data is trans-
ferred into four shift registers and shifted serially to the
output during the next 16-bit ADC cycle. Shift registers
are clocked by a serial clock that must be chosen fast
enough so that all data is shifted out before the next set
of data is loaded from the ADC. An all-zero pattern fol-
lows the data after all valid ADC data are streamed to the
output. A DATASYNC signal is used to signal the begin-
ning of each valid 16-bit data slice. In addition, there is a
TIME_SYNC signal that is output every 128 to 16,384
cycles of the ADC clock.
Maxim Integrated
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